1. Field of the Invention
This invention relates to a metal oxide semiconductor (MOS), and more particularly to a method for fabricating a high bias complementary MOS (CMOS).
2. Description of Related Art
As the size of semiconductor device is reduced, the channel length is accordingly reduced, resulting in a semiconductor device with a faster operational speed. However, even though the shorter channel length raises the operational speed, a channel length that is too short creates other serious problems. These problems are generally called the short channel effect and are described as follows. If the bias applied on the semiconductor device is kept constant but the channel length is shortened, according to a formula of "electric field (E-field)=bias/channel length", where E-field is measured in units of "V/m", the electrons within the channel gain more energy due to the stronger E-field so that the possibility of an electrical breakdown is higher.
In conventional methodology, a high bias MOS device usually employs an isolation layer and a drift region under the isolation layer to increase the distance between the source/drain regions and the gate. This allows the MOS device to work normally, even when a high bias is applied.
FIGS. 1A-1C are cross sectional views schematically illustrating some conventional high bias MOS devices.
In FIG. 1A, an N.sup.- doped region 101, an N.sup.+ doped region 102 and a gate layer 103 are formed on a semiconductor substrate such as a P.sup.- substrate 100. The N.sup.+ doped region 102 is the source/drain region. The N.sup.- doped region 101 is used to increase the distance between the source/drain region 102 and the gate 103.
FIG. 1B shows a P.sup.- substrate 110 with an N.sup.- doped region 111, an N.sup.+ doped region 112 for a source/drain region, a spacer 113 and a gate layer 114. The N.sup.- doped region 111 and the spacer 113 are used to increase the distance between the source/drain region 112 and the gate 114.
FIG. 1C shows a P.sup.- substrate 120 with an N.sup.- doped region 121, an N.sup.+ doped region 122 for source/drain region, a field oxide (FOX) 123 and a gate layer 124. The N.sup.- doped region 121 and spacer 123 are used to increase the distance between the source/drain region 122 and the gate 124.
The structures of the conventional high bias MOS devices shown in FIGS. 1A-1C are planar. To obtain an enough space for isolations between MOS devices, the planar dimension would have to be increased. This contradicts to the trend of reducing the critical dimension in semiconductor devices. This means that because the channel length in the conventional high bias MOS device can't be effectively reduced, the integration of a device is undermined so that a high bias MOS device can't be reduced in size to submicron dimensions.